Hello, I decided to make a thread for my 68010 microcomputer project. Here, I will post schematics, requests for help with certain circuits, as well as various musings about the project. Here are the planned system specs: Spoiler: Specs Processor: MC68010, 8 MHz Memory: 640K static RAM, 128K ROM BIOS, 64K kernel scratchpad or I/O area (read only in user mode), 192K kernel-exclusive memory (any access attempt will trip a bus error in user mode) = 1024K total memory Bus: 100-pin Direct Expansion Interface (DXI) - 24-bit address, 16-bit data, 8 IRQ's I/O: MC68450 DMA controller - two or four channels depending on model Virtual memory: no Peripherals: to be determined Operating system: ROM BASIC, some kind of 16/32-bit MS-DOS remake And here is where I need help: I need a bus timeout circuit. Here is how that works. Spoiler: Technical information ahead The circuit has one input, /AS. It drives two outputs, /TIMEOUT and /BERR. The CPU asserts /AS (drives it low) whenever it begins a bus cycle - including an interrupt acknowledge. It needs notification in the event of a bus error, which is done by grounding /BERR. A bus error includes access to an invalid address or a request to a device that is not ready (if /HALT is asserted by an external device when the bus error is signaled, the bus cycle will be retried when /HALT is negated; otherwise, an exception occurs). There needs to be some kind of time limit on how long /AS may be asserted; this ensures the system will not lock up due to an unresponsive device or spurious interrupt. By default, the bus timeout circuit places its outputs /TIMEOUT and /BERR into high impedance, as the lines are driven externally. However, if /AS is asserted for longer than, say, 50 milliseconds (about 400,000 clock cycles assuming my math is correct), the circuit will drive /BERR low. It will also drive /TIMEOUT low so that devices know that the bus error was not the result of a catastrophic failure, but a normal part of system operation. These outputs will be released to high impedance and the timer will be reset as soon as /AS is rescinded. UPDATE: problem solved! Here is my earliest progress on the CPU board: Your input is much appreciated!
Added the interrupt encoder. Some wires are colored for clarity - there is no color coding, it's just so you can see what's what. Next step is the interrupt acknowledge decoder - that will be much easier, as I won't have to pull any more lines high. The IRQ being acknowledged is encoded on pins A1-A3 (least significant bit on A1), so a simple 3-to-7 decoder will do the trick.
Behold the Super Orange Machine. It is a bus error timer. If /AS is asserted for longer than about 50 milliseconds, /TIMEOUT is asserted; and /TIMEOUT is rescinded, and the timer is reset by the PNP transistor, as soon as /AS is rescinded. UPDATE: there is an issue, DO NOT BUILD THE SUPORMA AS DEPICTED ABOVE! This is the correct schematic i hope UPDATE: The system actually features two Suporma's - the first one is the bus timeout, and the second one holds the CPU and external devices in the reset state for four seconds upon power-up. This gives everything time to stabilize its internal circuitry, plus it takes up more space in Ness' inventory for an added challenge.
